Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow

Lun Chun Wei*, Hung-Ming Chen, Li Da Huang, Sarah Songjie Xu

*Corresponding author for this work

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

As VLSI design complexity is continuously increasing, the yield loss due to via failure becomes more significant. Adding a redundant via adjacent to each single via is a well-known and highly recommended method to reduce yield loss due to via failure. In this paper, we develop a network-flow-based algorithm in post-layout stage for the redundant via insertion problem. With our novel and efficient approach, we can obtain optimal redundant via insertion solution in improving the manufacturing yield, with minimal fixup if necessary. Moreover, our approach is parallel-processing-friendly and effective in ECO incremental solution due to the nature of network-flow models.

原文English
主出版物標題GLSVLSI 2008
主出版物子標題Proceedings of the 2008 ACM Great Lakes Symposium on VLSI
頁面359-362
頁數4
DOIs
出版狀態Published - 1 十二月 2008
事件GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL, United States
持續時間: 4 三月 20086 三月 2008

出版系列

名字Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

ConferenceGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
國家United States
城市Orlando, FL
期間4/03/086/03/08

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