Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack

Dun Bao Ruan, Po-Tsun Liu*, Yu Chuan Chiu, Po Yi Kuo, Min Chin Yu, Kai Zhi Kan, Ta Chun Chien, Yi Heng Chen, Simon M. Sze

*Corresponding author for this work

研究成果: Article同行評審

10 引文 斯高帕斯(Scopus)

摘要

The amorphous indium gallium zinc oxide thin-film transistors (TFTs) with a multilayer high-k gate stack are investigated in this research. In order to achieve a high quality gate insulator for plastic flexible display application, the multilayer high-k gate stacks (SiO2/TiO2/HfO2) are deposited by a low-temperature physical vapor deposition (PVD) process. On the other hands, an interfacial layer between the high-k stack and metal oxide channel is important for the device performance. The effects of interfacial layer material (SiO2 or Ga2O3) are also discussed in this report. The devices with SiO2 interfacial layer show a high on/off current ratio of ~7 × 107 for its low gate leakage current, a small sub-threshold swing of 0.093 V/decade and a high field-effect mobility of ∼37.8 cm2/Vs for its good interface condition and low interface defeats. This research shows that the interface engineering of multilayer PVD gate stacks is necessary for oxide TFT fabrication.

原文English
頁(從 - 到)578-584
頁數7
期刊Thin Solid Films
660
DOIs
出版狀態Published - 30 八月 2018

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