Dynamic voltage domain assignment technique for low power performance manageable cell based design

Elone Lee*, Feng Tso Chien, Ching Hwa Cheng, Jiun-In  Guo

*Corresponding author for this work

研究成果: Conference contribution

摘要

Multi-voltage technique is an effective way to reduce power consumption. In the proposed voltage domain programmable (VDP) technique, high and low voltage domains applied to logic gates are programmable. The different voltage domains allow the chip performance and power consumption to be flexibly adjusted during circuit operation. In this proposed internal of the chip technique, the power switches possess the feature of flexible programming after chip manufacturing. The video decoder test chip proof of this novel methodology has 55% power reduction with good power-performance management mechanism.

原文English
主出版物標題2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
頁面359-360
頁數2
DOIs
出版狀態Published - 28 四月 2010
事件2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan
持續時間: 18 一月 201021 一月 2010

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
國家Taiwan
城市Taipei
期間18/01/1021/01/10

指紋 深入研究「Dynamic voltage domain assignment technique for low power performance manageable cell based design」主題。共同形成了獨特的指紋。

  • 引用此

    Lee, E., Chien, F. T., Cheng, C. H., & Guo, J-I. (2010). Dynamic voltage domain assignment technique for low power performance manageable cell based design. 於 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 (頁 359-360). [5419864] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2010.5419864