Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask

Hsin Chyh Hsu, Ming-Dou Ker

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

NMOS with dummy-gate structure is proposed to significantly improve electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, ESD current is discharged far away from the salicided surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level. The HBM (MM) ESD robustness of the NMOS with dummy-gate structure (W/L = 480 /spl mu/m/0.18 /spl mu/m) has been successfully improved from 0.5 kV (125 V) to 1.5 kV (325 V) in a 130-nm fully-salicided CMOS process. Under the same layout area of the gate-grounded NMOS (ggNMOS), HBM (MM) ESD level can be improved over 300% (260%) by the proposed dummy-gate structure. The proposed dummy-gate structure is fully processed compatible to general salicided CMOS processes without additional mask, which is very cost-efficient for application in the IC products.

原文English
主出版物標題Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006
頁面503-506
頁數4
DOIs
出版狀態Published - 1 十二月 2006
事件7th International Symposium on Quality Electronic Design, ISQED 2006 - San Jose, CA, United States
持續時間: 27 三月 200629 三月 2006

出版系列

名字Proceedings - International Symposium on Quality Electronic Design, ISQED
ISSN(列印)1948-3287
ISSN(電子)1948-3295

Conference

Conference7th International Symposium on Quality Electronic Design, ISQED 2006
國家United States
城市San Jose, CA
期間27/03/0629/03/06

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