Dual-vdd voltage island-aware buffered routing tree construction

Bruce Tseng*, Hung-Ming Chen

*Corresponding author for this work

研究成果: Article同行評審

摘要

Due to the necessity of low power methodology in VLSI and SoC designs, voltage island architecture is attracting attention in the design community. However, the corresponding EDA tools development regarding routing tree construction is still very few. Prior related studies focused on applying dual-Vdd buffers in routing tree construction, with the restriction on the ordering of buffers and the lack of level converter consideration. Therefore it cannot be applied directly on a design with voltage islands. This paper presents an algorithm to solve the buffer insertion and level converter assignment problem in the presence of voltage island in a low-power design. We have modified a dual-Vdd approach to be applied on those designs, then developed our method for comparison. With some greedy heuristics and prune techniques, our approach is very efficient and still keeps the quality of solutions. The experimental results show that we can obtain massive speedup and lower power solutions over a modified approach. Furthermore, as the number of sinks increases, a modified prior approach cannot find solutions within a reasonable CPU time, while our approach can find feasible solutions effectively.

原文English
頁(從 - 到)117-126
頁數10
期刊International Journal of Electrical Engineering
15
發行號2
出版狀態Published - 1 四月 2008

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