Direct tunneling RAM (DT-RAM) for high-density memory applications

Charles Kuo*, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

研究成果: Letter

3 引文 斯高帕斯(Scopus)

摘要

A new approach to reducing the tunnel oxide thickness in floating gate memories is introduced for RAM applications. Experimental measurements and two-dimensional (2-D) device simulations are used to investigate the operating principles of a direct tunneling RAM (DT-RAM) cell. DT-RAM targets memory applications in which manufacturability, scalability, low-power, high-density, and long retention times are important considerations.

原文English
頁(從 - 到)475-477
頁數3
期刊IEEE Electron Device Letters
24
發行號7
DOIs
出版狀態Published - 1 七月 2003

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