This paper presents a digital repetitive control scheme for the minimization of output voltage total harmonic distortion (THD) of a PWM inverter under large unknown nonlinear load. The multi-phase interleaved PWM inverter has been adopted to enhance the effective switching frequency as well as to share the load current. The realization of a digital control for PWM inverter, such as sampling delay and quantization error, may introduce many nonlinear effects to distort its output waveforms. A systematic design procedure is developed to minimize selected range of harmonic spectrum by shaping the output impedance by so that its output voltage THD can be lower than a specified value with given design constraints. The proposed control scheme has been realized with fully digital design by using a single-chip FPGA implementation and verified by using co-simulation technique via a VHDL simulator Modelsim combined with a system-level block diagram oriented simulator Simulink.