Differential cascode voltage switch with the pass-gate (DCVSPG) logic tree for high performance CMOS digital systems

F. S. Lai, W. Hwang

研究成果: Conference contribution同行評審

21 引文 斯高帕斯(Scopus)

摘要

A new circuit configuration, the differential cascode voltage switch with the pass-gate logic tree (DCVSPG), is presented. In this circuit family, we use the pass-gate logic tree to replace the nMOS logic tree in the conventional DCVS circuit in orderto eliminate the floating-node problem. By eliminating the floating-node, the DCVSPG shows superior performance, silicon area and power consumption. Moreover, the dynamic DCVSPG also provides the leverage of relieving the charge redistribution concern and reinforces the signal integrity in the typical pre-charge dynamic circuits. The principle of operation of the DCVSPG is explained. A simple synthesis technique of the pass-gate logic tree is discussed. Finally, a 64-bit carry look-ahead adder is designed by using ths static DCVSPG circuit. A nominal cycle time (Ta = 22°C and power supply of 2.5 V) of 2.0 ns is obtained by using a 0.5μm CMOS technology.

原文English
主出版物標題1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面358-362
頁數5
ISBN(電子)0780309782
DOIs
出版狀態Published - 1 一月 1993
事件1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan
持續時間: 12 五月 199314 五月 1993

出版系列

名字International Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN(列印)1930-8868

Conference

Conference1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
國家Taiwan
城市Taipei
期間12/05/9314/05/93

指紋 深入研究「Differential cascode voltage switch with the pass-gate (DCVSPG) logic tree for high performance CMOS digital systems」主題。共同形成了獨特的指紋。

引用此