Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process

Ming-Dou Ker*, Wen Yi Chen, Kuo Chun Hsu

*Corresponding author for this work

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

A new power-rail ESD clamp circuit in a 130-nm 1-V/2.5-V CMOS process for application in 3.3-V mixed-voltage I/O interface is proposed. The devices used in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage NMOS/PMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed to improve ESD robustness of the stacked NMOS by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.

原文English
主出版物標題2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual
頁面606-607
頁數2
DOIs
出版狀態Published - 15 十二月 2005
事件2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual - San Jose, CA, United States
持續時間: 17 四月 200521 四月 2005

出版系列

名字IEEE International Reliability Physics Symposium Proceedings
ISSN(列印)1541-7026

Conference

Conference2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual
國家United States
城市San Jose, CA
期間17/04/0521/04/05

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