Design of Power-Rail ESD Clamp with Dynamic Timing-Voltage Detection Against False Trigger during Fast Power-ON Events

Jie Ting Chen, Ming-Dou Ker*

*Corresponding author for this work

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

The RC-based power-rail electrostatic discharge (ESD) clamp with nMOS of large size has been widely utilized to enhance the ESD robustness of CMOS integrated circuits. However, such circuit design that only detects the rising time of ESD pulse may be accidentally triggered in some conditions, such as fast power-ON, hot-plug, and envelope tracking applications. In this paper, a new power-rail ESD clamp circuit with transient and voltage detection function has been proposed and implemented in a 0.18- mu m 1.8-V CMOS technology. The measurement results from the silicon chip have demonstrated that the new proposed power-rail ESD clamp circuit with adjustable minimum starting voltage (V) can achieve good ESD robustness and avoid triggering under fast power-ON condition. In addition, the proposed circuit has a low standby leakage current of 270 nA at 125 °C under normal power-ON condition.

原文English
頁(從 - 到)838-846
頁數9
期刊IEEE Transactions on Electron Devices
65
發行號3
DOIs
出版狀態Published - 1 三月 2018

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