Design of memory sub-system in H.264/AVC decoder

Chih Hung Li, Chang Hsuan Chang, Wen-Hsiao Peng, Wei Hwang, Tihao Chiang*

*Corresponding author for this work

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this paper, we present the memory sub-system of a H.264/AVC decoder designed for High profile and Level 4. Our design incorporates a synchronization buffer as a pre-cache buffer. We investigate the efficiency of DRAM access and power dissipation when the buffer is designed at different granularities. Statistical results show that the granularity of larger block size has higher memory efficiency, less access cycles and power dissipation. However, the granularity of 8×8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.

原文English
主出版物標題Digest of Technical Papers - 2007 International Conference on Consumer Electronics, ICCE 2007
DOIs
出版狀態Published - 24 八月 2007
事件2007 Digest of Technical Papers International Conference on Consumer Electronics - Las Vegas, NV, United States
持續時間: 10 一月 200714 一月 2007

出版系列

名字Digest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN(列印)0747-668X

Conference

Conference2007 Digest of Technical Papers International Conference on Consumer Electronics
國家United States
城市Las Vegas, NV
期間10/01/0714/01/07

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