This work focuses on the design of downlink receiver for future generation cellular systems. In the multipath division multiple access (MDMA) system, the initial synchronization process includes timing and carrier frequency synchronization as well as home cell search. For the proposed system, the user data is transmitted in time domain and the cell search is based on control signals transmitted in frequency domain simultaneously. Firstly, this paper presents a novel architecture for the joint detection and estimation of both the coarse symbol boundary and the fractional carrier frequency offset based on cyclic prefix in time domain. Secondly, a robust integer carrier frequency offset detection is performed with the primary control tone in frequency domain. Moreover, the position of the secondary control tones is used to obtain the cell ID. Finally, the preamble sequence carried by the secondary control tones is used to detect frame header through differential detection. The simulation results show the proposed synchronization algorithms can achieve detection failure rate less than 1% and the normalized residual carrier frequency offset is less than 5% under the interference of user data. Furthermore, a hardware design targeted at 200 Mbps per-user data rate is realized with memory arbiter to share memory.
|頁（從 - 到）||3211 - 3223|
|期刊||IEEE Transactions on Circuits and Systems I: Regular Papers|
|出版狀態||Accepted/In press - 1 一月 2020|