Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications

E. R. Hsieh, Y. S. Lin, Y. B. Zhao, C. H. Liu, Chao-Hsin Chien, Steve S. Chung

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

A new concept of the structure design with an alignment between the maximum band-to-band tunneling rate and electric field has been proposed to enhance the performance of TFETs. It was found that the specific gate of TFET to form an obtuse shape can dramatically improve the on-current of TFET, with over 4 order improvement in comparison to planar ones. This complementary TFET (CTFET) was also demonstrated by SRAM as a benchmark, with SiGe/Si integrated with III-V on Si substrate. In order to increase WNM and RSNM of CTFET SRAM, a new scheme has been adopted, in which SRAM has been successfully demonstrated with operating bias down to 0.3V.

原文English
主出版物標題2015 Silicon Nanoelectronics Workshop, SNW 2015
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9784863485389
出版狀態Published - 24 九月 2015
事件Silicon Nanoelectronics Workshop, SNW 2015 - Kyoto, Japan
持續時間: 14 六月 201515 六月 2015

出版系列

名字2015 Silicon Nanoelectronics Workshop, SNW 2015

Conference

ConferenceSilicon Nanoelectronics Workshop, SNW 2015
國家Japan
城市Kyoto
期間14/06/1515/06/15

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