Design of an FFT/IFFT processor for MIMO OFDM systems

Yu Wei Lin*, Chen-Yi Lee

*Corresponding author for this work

研究成果: Article同行評審

104 引文 斯高帕斯(Scopus)

摘要

In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/ IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-μm single-poly and eight-metal CMOS process. The core area is 660 × 2142 μm2, including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 μs meeting IEEE 802.11n standard requirements.

原文English
頁(從 - 到)807-815
頁數9
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
54
發行號4
DOIs
出版狀態Published - 1 四月 2007

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