Design, fabrication and calibration of a novel MEMS logic gate

Chun Yin Tsai, Tsung-Lin Chen

研究成果: Article同行評審

19 引文 斯高帕斯(Scopus)

摘要

This paper presents the design, fabrication and calibration of a novel MEMS logic gate that can perform Boolean algebra as well as logic devices composed of solid-state transistors. Unlike existing designs, the proposed design can perform either NAND gate or NOR gate functions using the same mechanical structure, but different electrical interconnects. The proposed design imposes three requirements on the fabrication process: two voltage levels carried on a suspended plate, metal-to-metal contact between shuttle electrodes and fixed electrodes, and a low process temperature (<300 °C). To fulfill these requirements, the residual stress in the fabricated device is substantial which could impair the functionality of the device. Therefore, a novel in situ film stress calibration method is developed to assist the development of the fabrication process. In a prototype design, the fabricated device is 250 μm long, 100 μm wide and of 3.97 μm gap. Experimental results show that the device can operate at 25/-25 V and 100 Hz, and achieve the proposed logic functions. In addition, several properties of this device are experimentally evaluated, including power consumption, on/off resistance, lifetime and resonant frequency.

原文English
文章編號095021
期刊Journal of Micromechanics and Microengineering
20
發行號9
DOIs
出版狀態Published - 1 九月 2010

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