Depletion-type cell-transistor on partial silicon-on-insulator substrate for 2×nm generation floating-gate NAND electrically erasable programmable read only memory

Makoto Mizukami*, Kiyohito Nishihara, Hirokazu Ishida, Fumiki Aiso, Tadashi Iguchi, Daigo Ichinose, Atsushi Fukumoto, Nobutoshi Aoki, Masaki Kondo, Takashi Izumida, Hiroyoshi Tanimoto, Toshiyuki Enda, Hiroshi Watanabe, Shuichi Toriyama, Takashi Suzuki, Ichiro Mizushima, Fumitaka Arai

*Corresponding author for this work

研究成果: Article同行評審

摘要

To reduce the short-channel effect for memory cell transistors beyond 2×nm cell size for NAND electrically erasable programmable read only memories (EEPROMs), we propose a depletion-type cell transistor fabricated on a self-manufactured partial silicon-on-insulator (SOI) substrate by conventional LSI process and solid-phase epitaxy. The memory cell transistors with stack-gate show good program/erase properties and have the good S-factor of 309 mV/decade, wide enough threshold voltage (V th ) window of 15 V between program and erase state, and fast enough program and erase time of 100 μs and 100 μs. And we observed no significant V th -window narrowing and increase in V th of about 1 V after 1000 cycling test. Operation bias sets of the depletion-type NAND EEPROM are as same as the sets of conventional NAND EEPROM and no peripheral circuit design change is needed. The short-channel effect is reduced substantially to available level for 2×nm size NAND EEPROM.

原文English
文章編號04DD09
期刊Japanese Journal of Applied Physics
49
發行號4 PART 2
DOIs
出版狀態Published - 1 四月 2010

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