Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in A 0.25-μM salicided CMOS process

Ming-Dou Ker*, Tai Xiang Lai

*Corresponding author for this work

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of Cable Discharge Event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been experimentally investigated in detail. All CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.25-μm salicided CMOS process to find optimum layout rules for CDE protection. From the measured results, the CDE robustness of CMOS devices is much worse than their HBM ESD robustness.

原文English
主出版物標題2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual
頁面633-634
頁數2
DOIs
出版狀態Published - 1 十二月 2006
事件44th Annual IEEE International Reliability Physics Symposium, IRPS 2006 - San Jose, CA, United States
持續時間: 26 三月 200630 三月 2006

出版系列

名字IEEE International Reliability Physics Symposium Proceedings
ISSN(列印)1541-7026

Conference

Conference44th Annual IEEE International Reliability Physics Symposium, IRPS 2006
國家United States
城市San Jose, CA
期間26/03/0630/03/06

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