Data reuse analysis of local stereo matching

Tsung Hsien Tsai*, Nelson Yen Chung Chang, Tian-Sheuan Chang

*Corresponding author for this work

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

External memory bandwidth and internal memory size have been major bottlenecks in designing VLSI architecture for real-time stereo matching hardware because of large amount of pixel data and disparity range. To address these bottlenecks, this work explores the impact of data reuse on disparity-order and pixel-order along with the partial column reuse (PCR) and vertically expanded row reuse (VERR) techniques we proposed. The analysis suggest that a disparity-order reuse with both PCR and VERR techniques is suitable for low memory cost and low external bandwidth design, whereas the pixel-order reuse with both techniques is more suitable for low computation resource requirement.

原文English
主出版物標題2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
頁面812-815
頁數4
DOIs
出版狀態Published - 19 九月 2008
事件2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
持續時間: 18 五月 200821 五月 2008

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
國家United States
城市Seattle, WA
期間18/05/0821/05/08

指紋 深入研究「Data reuse analysis of local stereo matching」主題。共同形成了獨特的指紋。

引用此