Data compression for EOS on-board SAR processor

C. Y. Chang*, Wai-Chi  Fang, J. C. Curlander

*Corresponding author for this work

研究成果: Paper同行評審

摘要

A lightweight, low-power, real-time data compressor design for the Earth Observing System (EOS) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-μm CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.

原文English
頁面1723-1728
頁數6
出版狀態Published - 1 十二月 1989
事件IGARSS'89 - Twelfth Canadian Symposium on Remote Sensing Part 3 (of 5) - Vancouver, BC, Can
持續時間: 10 七月 198914 七月 1989

Conference

ConferenceIGARSS'89 - Twelfth Canadian Symposium on Remote Sensing Part 3 (of 5)
城市Vancouver, BC, Can
期間10/07/8914/07/89

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