Plasmons in the highly doped source and drain regions of silicon field-effect transistors can strongly drag channel electrons via long-range collective Coulomb interactions and cause deteriorations in overall device performances. To examine such interactions, two different methods have been published: 1) sophisticated device simulations and 2) carefully calibrated experiments. To provide a more transparent understanding, we propose a third method in terms of two criteria: 1) one for the occurrence of the plasmon resonance and 2) the other for the strength of the plasmons. The former is determined based on our published dragged mobility data due to the interface plasmons and the bulk plasmons in gate. The latter makes use of our more recently experimentally extracted potential fluctuations due to plasmons in crystalline silicon. The effects of the temperature on the criteria are considered. It is a straightforward task to confirm that for a channel density larger than approximately 5 x 10(12) cm(-2), the source and drain plasmons act as key limiters in silicon device scaling. Therefore, the underlying device physics, modeling, simulations, experimental analyses, and data interpretation may be inaccurate if the limiting factors are not incorporated.