Continuous-flow parallel bit-reversal circuit for MDF and MDC FFT architectures

Sau-Gee Chen*, Shen Jui Huang, Mario Garrido, Shyh-Jye Jou

*Corresponding author for this work

研究成果: Article同行評審

21 引文 斯高帕斯(Scopus)

摘要

This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.

原文English
文章編號6849501
頁(從 - 到)2869-2877
頁數9
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
61
發行號10
DOIs
出版狀態Published - 1 十月 2014

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