Compact models for sub-22nm MOSFETs

Y. S. Chauhan*, D. D. Lu, S. Venugopalan, M. A. Karim, A. Niknejad, Chen-Ming Hu

*Corresponding author for this work

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

FinFET and UTBSOI (or ETSOI) FET are the two promising multi-gate FET candidates for sub-22nm CMOS technology. The BSIM-CMG and BSIM-IMG are the surface potential based physical compact models for multi-gate MOSFETs. The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFET. The BSIM-IMG model has been developed to model independent double-gate MOSFET capturing threshold voltage variation with back gate bias. Both models have been verified by simulation /measurements and show excellent results for all types of real device effects like SCE, DIBL, mobility degradation, poly depletion, QME etc.

原文English
主出版物標題Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
頁面720-725
頁數6
出版狀態Published - 23 十一月 2011
事件Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011 - Boston, MA, United States
持續時間: 13 六月 201116 六月 2011

出版系列

名字Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
2

Conference

ConferenceNanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
國家United States
城市Boston, MA
期間13/06/1116/06/11

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