Common-centroid FinFET placement considering the impact of gate misalignment

Po Hsun Wu, Po-Hung Lin, X. Li, Tsung Yi Ho

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

The FinFET technology has been regarded as a better alternative among different device technologies at 22nm node and beyond due to more effective channel control and lower power consumption. However, the gate misalignment problem resulting from process variation based on the FinFET technology becomes even severer compared with the conventional planar CMOS technology. Such misalignment may increase the threshold voltage and decrease the drain current of a single transistor. When applying the FinFET technology to analog circuit design, the variation of drain currents will destroy the current matching among transistors and degrade the circuit performance. In this paper, we present the first FinFET placement technique for analog circuits considering the impact of gate misalignment together with systematic and random mismatch. Experimental results show that the proposed algorithms can obtain an optimized common-centroid FinFET placement with much better current matching.

原文English
主出版物標題ISPD 2015 - Proceedings of the ACM International Symposium on Physical Design 2015
發行者Association for Computing Machinery
頁面25-31
頁數7
ISBN(電子)9781450333993
DOIs
出版狀態Published - 29 三月 2015
事件18th ACM International Symposium on Physical Design, ISPD 2015 - Monterey, United States
持續時間: 29 三月 20151 四月 2015

出版系列

名字Proceedings of the International Symposium on Physical Design
29-March-2015

Conference

Conference18th ACM International Symposium on Physical Design, ISPD 2015
國家United States
城市Monterey
期間29/03/151/04/15

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