Challenges for future semiconductor manufacturing

Hiroshi Iwai*, Kuniyuki Kakushima, Hei Wong

*Corresponding author for this work

研究成果: Article同行評審

20 引文 斯高帕斯(Scopus)

摘要

The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

原文English
頁(從 - 到)43-81
頁數39
期刊International Journal of High Speed Electronics and Systems
16
發行號1
DOIs
出版狀態Published - 三月 2006

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