Cellular automata based hardware accelerator for parallel maze routing

Shashank Saurabh, Kuen Wey Lin, Yih-Lang Li

研究成果: Conference contribution同行評審

摘要

This paper introduces a scalable hardware design to accelerate the maze algorithm for VLSI routing on Cellular automata (CA). The time-complexities of wave-propagation and back-tracing on CA are both O(n) while constant time for label clearing. Innately high parallelism of CA largely reduces the runtime in wave propagation and label clearing. The RTL implementation for this design has been developed in Verilog and a cell lattice of 35×35 cells has been implemented on FPGA. The runtime of the proposed CA is shorter than that on a sequential computer by about four to five orders of magnitude.

原文English
主出版物標題Proceedings of the IEEE International Conference on Advanced Materials for Science and Engineering
主出版物子標題Innovation, Science and Engineering, IEEE-ICAMSE 2016
編輯Teen-Hang Meen, Stephen D. Prior, Artde Donald Kin-Tak Lam
發行者Institute of Electrical and Electronics Engineers Inc.
頁面680-683
頁數4
ISBN(電子)9781509038695
DOIs
出版狀態Published - 2 二月 2017
事件2016 IEEE International Conference on Advanced Materials for Science and Engineering, IEEE-ICAMSE 2016 - Tainan, Taiwan
持續時間: 12 十一月 201613 十一月 2016

出版系列

名字Proceedings of the IEEE International Conference on Advanced Materials for Science and Engineering: Innovation, Science and Engineering, IEEE-ICAMSE 2016

Conference

Conference2016 IEEE International Conference on Advanced Materials for Science and Engineering, IEEE-ICAMSE 2016
國家Taiwan
城市Tainan
期間12/11/1613/11/16

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