@inproceedings{e31a8bcd2a1e4bb0bc90eecefd1c4b6f,
title = "Cellular automata based hardware accelerator for parallel maze routing",
abstract = "This paper introduces a scalable hardware design to accelerate the maze algorithm for VLSI routing on Cellular automata (CA). The time-complexities of wave-propagation and back-tracing on CA are both O(n) while constant time for label clearing. Innately high parallelism of CA largely reduces the runtime in wave propagation and label clearing. The RTL implementation for this design has been developed in Verilog and a cell lattice of 35×35 cells has been implemented on FPGA. The runtime of the proposed CA is shorter than that on a sequential computer by about four to five orders of magnitude.",
keywords = "cellular automata, hardware accelerator, maze routing",
author = "Shashank Saurabh and Lin, {Kuen Wey} and Yih-Lang Li",
year = "2017",
month = feb,
day = "2",
doi = "10.1109/ICAMSE.2016.7840214",
language = "English",
series = "Proceedings of the IEEE International Conference on Advanced Materials for Science and Engineering: Innovation, Science and Engineering, IEEE-ICAMSE 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "680--683",
editor = "Teen-Hang Meen and Prior, {Stephen D.} and Lam, {Artde Donald Kin-Tak}",
booktitle = "Proceedings of the IEEE International Conference on Advanced Materials for Science and Engineering",
address = "United States",
note = "null ; Conference date: 12-11-2016 Through 13-11-2016",
}