BSIM4 gate leakage model including source-drain partition

K. M. Cao*, W. C. Lee, W. Liu, X. Jin, Pin Su, S. K.H. Fung, J. X. An, B. Yu, Chen-Ming Hu

*Corresponding author for this work

研究成果: Conference article同行評審

155 引文 斯高帕斯(Scopus)

摘要

Gate dielectric leakage current becomes a serious concern as sub-20Å gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.

原文English
頁(從 - 到)815-818
頁數4
期刊Technical Digest - International Electron Devices Meeting
DOIs
出版狀態Published - 1 十二月 2000
事件2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
持續時間: 10 十二月 200013 十二月 2000

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