Background calibration of integrator leakage in discrete-time delta-sigma modulators

Su Hao Wu*, Jieh-Tsorng Wu

*Corresponding author for this work

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper presents an integration-leakage calibration technique for the switched-capacitor integrators in a delta-sigma modulator (DSM). Integrators realized with low-gain opamps are lossy. A DSM that uses lossy integrators exhibits a degraded signal-to-quantization-noise ratio. To calibrate an integrator, its integration leakage is detected in the digital domain, and the leakage compensation is applied to the same integrator in the analog domain. The proposed scheme can calibrate all integrators in a discrete-time DSM of any form. It can be proceed in the background without interrupting the normal DSM operation. The design considerations for the proposed calibration scheme are discussed. Design cases of a 1st-order, a 2nd-order, and a 3rd-order DSM are demonstrated and simulated.

原文English
頁(從 - 到)645-655
頁數11
期刊Analog Integrated Circuits and Signal Processing
81
發行號3
DOIs
出版狀態Published - 2 十二月 2014

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