Automatic verification stimulus generation for interface protocols modeled with non-deterministic extended FSM

Che Hua Shih*, Juinn-Dar Huang, Jing Yang Jou

*Corresponding author for this work

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

Verifying if an integrated component is compliant with certain interface protocol is a vital issue in component-based system-on-a-chip (SoC) designs. For simulation-based verification, generating massive constrained simulation stimuli is becoming crucial to achieve a high verification quality. To further improve the quality, stimulus biasing techniques are often used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the non-deterministic extended finite-state machine (NEFSM), and then propose an automatic stimulus generation approach based on it. This approach is capable of providing numerous biasing strategies. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme.

原文English
文章編號4799218
頁(從 - 到)723-727
頁數5
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
17
發行號5
DOIs
出版狀態Published - 1 五月 2009

指紋 深入研究「Automatic verification stimulus generation for interface protocols modeled with non-deterministic extended FSM」主題。共同形成了獨特的指紋。

引用此