Asymmetrical Characteristics in LDD and Minimum-Overlap MOSFET's

T. Y. Chan, A. T. Wu, P. K. Ko, Chen-Ming Hu, Reda R. Razouk

研究成果: Article

34 引文 斯高帕斯(Scopus)

摘要

An asymmetrical drain, substrate, and gate current phenomenon with respect to drain-source reversal in short-channel lightly doped-drain (LDD) and minimum-overlap MOSFET has been observed. By controlled device fabrication splits, it is confirmed that these asymmetrical device characteristics are caused by the 7° off-axis drain-source implant which creates different degrees of offset between the gate edge and the source-drain junctions. The offset degrades the 1-V characteristics. Substrate and gate current asymmetries are studied by analyzing the channel electrical field using two-dimensional device simulations. High-channel field at the source end is proposed to explain the second hump in the double-humped substrate current characteristic and the strong gate current injection when the devices are operated with the nonoverlap side as the source. One way to avoid the shadowing effect at ion implantation is to etch the poly-gate side wall to a small positive bevel angle.

原文English
頁(從 - 到)16-19
頁數4
期刊IEEE Electron Device Letters
7
發行號1
DOIs
出版狀態Published - 1 一月 1986

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