Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection

Ming-Dou Ker*

*Corresponding author for this work

研究成果: Paper同行評審

13 引文 斯高帕斯(Scopus)

摘要

A novel substrate-triggering field-oxide device (STFOD) is proposed to form an area-efficient ESD clamp circuit for whole-chip ESD protection in submicron CMOS technology. Experimental results in a 0.6-μm CMOS process have verified that this STFOD can provide four-times higher ESD robustness in per unit layout area as comparing to the previous works with the NMOS device. This design has been practically implemented in an 8-bits DAC chip to provide a real whole-chip ESD protection of above 4 KV.

原文English
頁面69-73
頁數5
DOIs
出版狀態Published - 1 一月 1997
事件Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
持續時間: 3 六月 19975 六月 1997

Conference

ConferenceProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
城市Taipei, China
期間3/06/975/06/97

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