Architecture design of QPP interleaver for parallel turbo decoding

Shuenn Gi Lee*, Chung-Hsuan Wang, Wern Ho Sheen

*Corresponding author for this work

研究成果: Conference contribution同行評審

7 引文 斯高帕斯(Scopus)

摘要

Quadratic permutation polynomial (QPP) interleaver has the advantage of contention-free for parallel memory access and has been adopted in the 3GPP LTE for turbo coding. Conventional implementations of the QPP interleaver based on the look-up table or on-line calculation usually result in large circuit area or higher clock rate for parallel turbo decoding. In this paper, an architecture design of QPP interleaver for parallel turbo decoding is presented which can provide parallel memory access without extra storage of interleaving patterns or the increment of clock rate compared with the conventional approaches. The proposed design is also reconfigurable for variable interleaver lengths.

原文English
主出版物標題2010 IEEE 71st Vehicular Technology
DOIs
出版狀態Published - 30 七月 2010
事件2010 IEEE 71st Vehicular Technology Conference, VTC 2010-Spring - Taipei, Taiwan
持續時間: 16 五月 201019 五月 2010

出版系列

名字IEEE Vehicular Technology Conference
ISSN(列印)1550-2252

Conference

Conference2010 IEEE 71st Vehicular Technology Conference, VTC 2010-Spring
國家Taiwan
城市Taipei
期間16/05/1019/05/10

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