Architecture design of MPEG-4 texture decoder supporting object-based video coding

Hui Cheng Hsu*, N. Y C Chang, Tian-Sheuan Chang

*Corresponding author for this work

研究成果: Conference contribution同行評審

摘要

Handling of the complexity which arises due the irregularity data nature for MPEG-4 object based video coding is an important issue in MPEG-4 texture decoder design. Another crucial issue is designing an efficient architecture to satisfy the resource sensitive nature of portable embedded video codec systems. This paper presents an architecture for texture decoding to address these two major issues. By adopting zero-skipping and zero index tables together, the throughput and power consumption are improved significantly. To avoid incurring extra hardware overhead, multiplication sharing and buffer sharing are also incorporated. The synthesized design can perform texture decoding of CIF@30FPS under 2.18 MHz. using UMC 0.18μm 1P6M technology, the reported power consumption is 0.92 mW.

原文English
主出版物標題2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
頁面275-278
頁數4
DOIs
出版狀態Published - 1 十二月 2005
事件2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
持續時間: 27 四月 200529 四月 2005

出版系列

名字2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
國家Taiwan
城市Hsinchu
期間27/04/0529/04/05

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