Architecture design of belief propagation for real-time disparity estimation

Yu Cheng Tseng*, Tian-Sheuan Chang

*Corresponding author for this work

研究成果: Article

6 引文 斯高帕斯(Scopus)

摘要

Belief propagation based algorithms perform best in disparity estimation but suffer from high computational complexity and storage, especially in message passing. This paper proposes an efficient architecture design with three techniques to solve the problems. For the memory storage, we propose the spinning-message and the sliding-bipartite node plane that can reduce memory cost to 1.2% for image-scale algorithms and 23.4% for block-scale algorithms, when compared to the traditional approach. For the logic complexity, we propose a buffer-free processing element architecture that has 3.6 times hardware efficiency of the previous work. The three proposed techniques could be applied to various belief propagation based algorithms to save significant hardware cost as well as approach real-time speed.

原文English
文章編號5604299
頁(從 - 到)1555-1564
頁數10
期刊IEEE Transactions on Circuits and Systems for Video Technology
20
發行號11
DOIs
出版狀態Published - 1 十一月 2010

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