Application of semiclassical device simulation to trade-off studies for sub-0.1 μm MOSFETs

Claudio Fiegna*, Hiroshi Iwai, Masanobu Saito, Enrico Sangiorgi

*Corresponding author for this work

研究成果: Conference article

10 引文 斯高帕斯(Scopus)

摘要

In this work, applicability of established semiclassical (SC) simulation techniques to ultra-short gate MOS devices is discussed and comparisons between experimental data of MOS transistors with gate down to 40 nm and simulation results are reported. Finally, examples of applications to the comparison of different device structures are reported.

原文English
頁(從 - 到)347-350
頁數4
期刊Technical Digest - International Electron Devices Meeting
DOIs
出版狀態Published - 1994
事件Proceedings of the 1994 IEEE International Electron Devices Meeting - San Francisco, CA, USA
持續時間: 11 十二月 199414 十二月 1994

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