Analysis of application of the IDDQ technique to the deep sub-micron VLSI testing

Chih Wen Lu, Chung Len Lee, Chauchin Su, Jwu E. Chen

研究成果: Article

1 引文 斯高帕斯(Scopus)

摘要

In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 × 107 gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.

原文English
文章編號389110
頁(從 - 到)89-97
頁數9
期刊Journal of Electronic Testing: Theory and Applications (JETTA)
18
發行號1
DOIs
出版狀態Published - 1 一月 2002

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