Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance - Part II: Model Validation

Girish Pahwa, Tapas Dutta, Amit Agarwal, Sourabh Khandelwal, Sayeef Salahuddin, Chen-Ming Hu, Yogesh Singh Chauhan

研究成果: Article

73 引文 斯高帕斯(Scopus)

摘要

In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation.

原文English
文章編號7590009
頁(從 - 到)4986-4992
頁數7
期刊IEEE Transactions on Electron Devices
63
發行號12
DOIs
出版狀態Published - 1 十二月 2016

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