An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design

Boyu Hu*, Yuan Du, Rulin Huang, Jeffrey Lee, Young Kai Chen, Mau-Chung Chang

*Corresponding author for this work

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed in terms of its speed, power consumption, and linearity. A voltage-mode PAM-4 transmitter with 2-tap FFE utilizing the proposed architecture is implemented in the 65-nm CMOS technology. It achieves a data rate of 34 Gb/s and an energy efficiency of 2.7 mW/Gb/s.

原文English
文章編號8012497
頁(從 - 到)3260-3264
頁數5
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
25
發行號11
DOIs
出版狀態Published - 1 十一月 2017

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