An online thermal-constrained task scheduler for 3D multi-core processors

Chien Hui Liao, Charles H.P. Wen, Krishnendu Chakrabarty

研究成果: Conference contribution

12 引文 斯高帕斯(Scopus)

摘要

Hotspots occur frequently in 3D multi-core processors (3D-MCPs) and they can adversely impact system reliability and lifetime. Moreover, frequent occurrences of hotspots lead to more dynamic voltage and frequency scaling (DVFS), resulting in degraded throughput. Therefore, a new thermal-constrained task scheduler based on thermal-pattern-aware voltage assignment (TPAVA) is proposed in this paper. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. Moreover, the proposed task scheduler integrates a vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs. Experimental results show that, compared with two previous methods, the proposed task scheduler can respectively lower hotspot occurrences by 47.13% and 53.91%, and improve throughput by 6.50% and 32.06%. As a result, TPAVA and VGVS are effectively for reducing occurrences of hotspots and optimizing throughput for 3D-MCPs under thermal constraints.

原文English
主出版物標題Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
發行者Institute of Electrical and Electronics Engineers Inc.
頁面351-356
頁數6
ISBN(電子)9783981537048
DOIs
出版狀態Published - 22 四月 2015
事件2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 - Grenoble, France
持續時間: 9 三月 201513 三月 2015

出版系列

名字Proceedings -Design, Automation and Test in Europe, DATE
2015-April
ISSN(列印)1530-1591

Conference

Conference2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
國家France
城市Grenoble
期間9/03/1513/03/15

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