This paper presents an efficient VLSI architecture of shape-adaptive inverse discrete cosine transform (SA-IDCT) for the MPEG-4 video system. The proposed architecture contains a cost-effective 1-D variable-length IDCT engine and an auto-aligned transpose memory organization. The proposed design exploits the properties of SA-IDCT transform matrix to reduce area and improve throughput. Besides, the auto-aligned transpose memory organization can achieve transposing, shifting and aligning simultaneously with the capability of zero skipping. Compared to other designs, our architecture has higher throughout and lower power dissipation. When clocking at 62.5 MHz, the proposed architecture has a throughput of 401.41Mpixels/sec and power dissipation of 5.56 mW/sample @ 1.8V, 62.5MHz.
|出版狀態||Published - 1 十二月 2004|
|事件||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan|
持續時間: 6 十二月 2004 → 9 十二月 2004
|Conference||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology|
|期間||6/12/04 → 9/12/04|