An investigation of strain silicon technology on highly strained, highly scaled nfet devices

Chih Cheng Lu*, Tan Fu Lei, Tuo-Hung Hou, Chao-Hsin Chien, M. H. Liao, T. L. Lee, S. M. Jang

*Corresponding author for this work

研究成果: Article同行評審

摘要

In this paper, we've investigated the limitation of strained silicon technology and explored the reason why nFET Id-sat enhancement ratio becomes less sensitive to the capping nitride stress when the nFET device is highly scaled into the next generation technology node. Nanoscale bulk nFET device DC performance is experimentally measured, and then explained with the aid of ballistic transport behavior. The extracted ballistic efficiency increased with the reduction of the device channel-length as expected. Moreover, we've provided a simple view of the essential physics of carrier transport in nanoscale MOS transistors, in spite of the complex non-local transport that occurs in such scaled devices. Results in our work provide not only an insight for strained silicon mobility behaviors on highly scaled devices, but also a guidance to keep devices consistently enhanced to meet ever challenging device performance targets.

原文English
頁(從 - 到)289-294
頁數6
期刊International Journal of Electrical Engineering
16
發行號4
出版狀態Published - 1 八月 2009

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