An in/post-loop deblocking filter with hybrid filtering schedule

Tsu Ming Liu*, Wen Ping Lee, Chen-Yi Lee

*Corresponding author for this work

研究成果: Article同行評審

37 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose a high-throughput deblocking filter to perform the in-loop or post-loop filtering process for different standard requirements. The performance improvement is very mild if we replace a post-loop filter with an in-loop filter. To alleviate this problem, we derive an integration-oriented algorithm that can be reconfigured as the in-loop or post-loop filter. Moreover, we develop a hybrid filtering schedule to reach a lower bound of processing cycles. In particular, we reschedule the filtering order and reuse the intermediate pixels when the deblocking filter switches the filtered edges from vertical to horizontal direction. Finally, a 0.18-μm CMOS design that performs the in/post-loop filter with the hybrid filtering schedule is implemented. The synthesized gate counts are 21.1 K which is reduced to 70% of preliminary design that performs the in-loop or post-loop filter separately. Moreover, it achieves 4×10 5 macroblock/s of throughput rate at a 100-MHz clock rate.

原文English
文章編號4265632
頁(從 - 到)937-943
頁數7
期刊IEEE Transactions on Circuits and Systems for Video Technology
17
發行號7
DOIs
出版狀態Published - 1 七月 2007

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