An indexed-scaling pipelined FFT processor for OFDM-based WPAN applications

Yuan Chen*, Yu Chi Tsao, Yu Wei Lin, Chin Hung Lin, Chen-Yi Lee

*Corresponding author for this work

研究成果: Article同行評審

53 引文 斯高帕斯(Scopus)

摘要

In this brief, a high-throughput and low-complexity fast Fourier transform (FFT) processor for wideband orthogonal frequency division multiplexing communication systems is presented. A new indexed-scaling method is proposed to reduce both the critical-path delay and hardware cost by employing shorter wordlength. Together with the mixed-radix multipath delay feedback structure, the proposed FFT processor can achieve very high throughput with low hardware cost. From analysis, it is shown that the proposed indexed-scaling method can save at least 11% memory utilizations compared to other state-of-the-art scaling algorithms. Also, a test chip of a 1.2 Gsample/s 2048-point FFT processor has been designed using UMC 90-nm 1P9M process with a core area of 0.97 mm2. The signal-to-quantization-noise ratio (SQNR) performance of this test chip is over 32.7 dB to support 16-QAM modulation and the power consumption is about 117 mW at 300 MHz. Compared to the fixed-point FFT processors, about 26% area and 28% power can be saved under the same throughput and SQNR specifications.

原文English
頁(從 - 到)146-150
頁數5
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
55
發行號2
DOIs
出版狀態Published - 1 十二月 2008

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