An incremental aging analysis method based on delta circuit simulation technique

Si Rong He, Nguyen Cao Qui, Yu Hsuan Kuo, Chien-Nan Liu

研究成果: Conference contribution

摘要

With the advance of VLSI technology, the parameter shift due to device aging has increasingly impacts on the circuit yield and reliability. Because the aging effects may degrade circuit performance and cause circuit failure after a period of time, aging analysis is also required in the design flow to avoid reliability issues. Previous aging analysis approaches often have a trade-off between accuracy and simulation time. In order to improve the efficiency of aging analysis while keeping high accuracy, this paper proposes an incremental simulation technique based on delta circuit models. Since aging process is often a gradual change, incremental simulation technique is very effective to reduce the simulation time of each iteration with almost the same accuracy. Furthermore, a dynamic aging sampling technique is also proposed to further improve the efficiency of aging analysis with little accuracy loss. As demonstrated in the experiments, the proposed approach is indeed an effective way to reduce the aging analysis time while keeping estimation accuracy.

原文English
主出版物標題Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017
發行者IEEE Computer Society
頁面60-65
頁數6
ISBN(電子)9781538624364
DOIs
出版狀態Published - 24 一月 2018
事件26th IEEE Asian Test Symposium, ATS 2017 - Taipei, Taiwan
持續時間: 27 十一月 201730 十一月 2017

出版系列

名字Proceedings of the Asian Test Symposium
ISSN(列印)1081-7735

Conference

Conference26th IEEE Asian Test Symposium, ATS 2017
國家Taiwan
城市Taipei
期間27/11/1730/11/17

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  • 引用此

    He, S. R., Qui, N. C., Kuo, Y. H., & Liu, C-N. (2018). An incremental aging analysis method based on delta circuit simulation technique. 於 Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017 (頁 60-65). (Proceedings of the Asian Test Symposium). IEEE Computer Society. https://doi.org/10.1109/ATS.2017.24