This paper proposes an efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. The proposed direct 2-D transform coding design eliminates the data transposition registers to greatly increase the data processing rate and reduce the hardware cost. When comparing the proposed design with the existing designs, the proposed design owns over 90% higher hardware efficiency through the measure of DTUA (Data Throughput per Unit Area) for computing the multi-transform in MPEG-4 AVC/H.264. By using a 0.18-μm CMOS technology, the optimum operating clock frequency of the proposed multitransform design is 100 MHz, which achieves 800M pixels/sec data throughput rate with the area cost of 6482 gates. Moreover, the proposed design balances the I/O data rate and processing rate through an interlaced I/O schedule.
|頁（從 - 到）||4517-4520|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1 十二月 2005|
|事件||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
持續時間: 23 五月 2005 → 26 五月 2005