An all-digital phase locked loop (ADPLL) with cascaded dynamic phase average (DPA) loop for wide multiplication range applications is presented in this paper. The multiplication factor can range from 4 to 65025 (255 × 255). The proposed architecture involves a minimum of hardware and improves jitter performance to reduce the noise and jitter associated with input reference. The dynamic phase averaging (DPA) loop control employing digital phase estimators (DPE) enhances frequency detection resolution and loop stability. A (Q.R) vector counter and an additional state counter serve as phase estimators. The proposed ADPLL includes cascaded DPA loops: the first stage is low frequency loop and the second stage is high frequency loop. A proto-type chip has been implemented with 0.18μm 1P6M CMOS process that can operate from 2MHz to 500MHz. The input frequency ranges from 5KHz to 50MHz. Thus it not only reduces the cost and design complexity of ADPLL, but also offers particular advantages for wide multiplication range applications.
|頁（從 - 到）||4875-4878|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1 十二月 2005|
|事件||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
持續時間: 23 五月 2005 → 26 五月 2005