An algorithm for calculating the lower confidence bounds of CPU and CPL with application to low-drop-out linear regulators

W.l. Pearn*, Ming Hung Shu

*Corresponding author for this work

研究成果: Article同行評審

18 引文 斯高帕斯(Scopus)

摘要

In assessing the performance of normal stable manufacturing processes with one-sided specification limits, process capability indices CPU and CPL have been widely used to measure the process capability. The purpose of this paper is to develop an algorithm to compute the lower confidence bounds on CPU and CPL using the UMVUEs of CPU and CPL. The lower confidence bound presents a measure on the minimum capability of the process based on the sample data. We also provide tables for the engineers/practitioners to use in measuring their processes. A real-world example taken from a microelectronics device manufacturing process is investigated to illustrate the applicability of the algorithm. Implementation of the existing statistical theory for capability assessment fills the gap between the theoretical development and the in-plant applications.

原文English
頁(從 - 到)495-502
頁數8
期刊Microelectronics Reliability
43
發行號3
DOIs
出版狀態Published - 1 三月 2003

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