An 865-μW H.264/AVC video decoder for mobile applications

Tsu Ming Liu*, Ting An Lin, Sheng Zen Wang, Wen Ping Lee, Kang Cheng Hou, Jiun Yan Yang, Chen Yi Lee

*Corresponding author for this work

研究成果: Conference contribution同行評審

24 引文 斯高帕斯(Scopus)

摘要

A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quarter-common intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865μW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on 4×4 sub-block level pipelining that achieves better buffer allocation and decoding throughput. In addition, several modules are designed with new features to improve overall system throughput (up to 260,000 Macro-Block/sec). The proposed solution integrates 456-k logic gates with 161Kb of embedded SRAM in 0.18-μm single-poly six-metal CMOS process with area of 11.3mm2.

原文English
主出版物標題2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
發行者IEEE Computer Society
頁面301-304
頁數4
ISBN(列印)0780391624, 9780780391628
DOIs
出版狀態Published - 1 一月 2005
事件1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan
持續時間: 1 十一月 20053 十一月 2005

出版系列

名字2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Conference

Conference1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
國家Taiwan
城市Hsinchu
期間1/11/053/11/05

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