An 81.6 μw FastICA processor for epileptic seizure detection

Chia Hsiang Yang*, Yi Hsin Shih, Her-Ming Chiueh

*Corresponding author for this work

研究成果: Article同行評審

21 引文 斯高帕斯(Scopus)

摘要

To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. To reduce the energy dissipation, eigenvalue decomposition (EVD) is utilized in the preprocessing stage to reduce the convergence time of iterative calculation of ICA components. EVD is computed efficiently through an array structure of processing elements running in parallel. Area-efficient EVD architecture is realized by leveraging the approximate Jacobi algorithm, leading to a 77.2% area reduction. By choosing proper memory element and reduced wordlength, the power and area of storage memory are reduced by 95.6% and 51.7%, respectively. The chip area is minimized through fixed-point implementation and architectural transformations. Given a latency constraint of 0.1 s, an 86.5% area reduction is achieved compared to the direct-mapped architecture. Fabricated in 90 nm CMOS, the core area of the chip is 0.40 . The FastICA processor, part of an integrated epileptic control SoC, dissipates 81.6 at 0.32 V. The computation delay of a frame of 256 samples for 8 channels is 84.2 ms. Compared to prior work, 0.5% power dissipation, 26.7% silicon area, and 3.4 computation speedup are achieved. The performance of the chip was verified by human dataset.

原文English
文章編號6842700
頁(從 - 到)60-71
頁數12
期刊IEEE Transactions on Biomedical Circuits and Systems
9
發行號1
DOIs
出版狀態Published - 1 二月 2015

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