An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC with Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen Cheng Kuan*, Mau Chung Frank Chang, Jieh-Tsorng Wu, Shiuh Hua Wood Chiang

*Corresponding author for this work

研究成果: Article同行評審

摘要

An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than 2× improvement from the state-of-the-art.

原文English
文章編號8877924
頁(從 - 到)83-86
頁數4
期刊IEEE Solid-State Circuits Letters
2
發行號9
DOIs
出版狀態Published - 九月 2019

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