An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC with Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen Cheng Kuan, Mau Chung Frank Chang, Jieh Tsorng Wu*, Shiuh Hua Wood Chiang

*Corresponding author for this work

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW,yielding an FoM of 37 fJ/conv.-step,the lowest among the reported ADCs with similar speeds and resolutions and more than 2× improvement from the state-of-the-art.

原文English
主出版物標題ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
發行者Institute of Electrical and Electronics Engineers Inc.
頁面83-86
頁數4
ISBN(電子)9781728115504
DOIs
出版狀態Published - 九月 2019
事件45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 - Cracow, Poland
持續時間: 23 九月 201926 九月 2019

出版系列

名字ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

Conference

Conference45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
國家Poland
城市Cracow
期間23/09/1926/09/19

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